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1 lt1055/lt1056 10556fc precision, high speed, jfet input operational amplifiers + 0v to 10v input 10khz trim 5k 4.7k 15v 2n3906 15v ?5v lt1055/56 ta01 ?5v = 1n4148 3m 0.001 (polystyrene) 0.1 f the low offset voltage of lt1056 contributes only 0.1hz of error while its high slew rate permits 10khz operation. 0.1 f 22k 75k 1.5k lm329 3.3m 7 6 4 3 2 33pf *1% film output 1hz to 10khz 0.005% linearity lt1056 guaranteed offset voltage: 150 v max ?5 c to 125 c: 500 v max guaranteed drift: 4 v/ c max guaranteed bias current 70 c: 150pa max 125 c: 2.5na max guaranteed slew rate: 12v/ s min available in 8-pin pdip and so packages precision, high speed instrumentation logarithmic amplifiers d/a output amplifiers photodiode amplifiers voltage-to-frequency converters frequency-to-voltage converters fast, precision sample-and-hold the lt 1055/lt1056 jfet input operational amplifiers combine precision specifications with high speed perfor- mance. for the first time, 16v/ s slew rate and 6.5mhz gain bandwidth product are simultaneously achieved with off- set voltage of typically 50 v, 1.2 v/ c drift, bias currents of 40pa at 70 c and 500pa at 125 c. the 150 v maximum offset voltage specification is the best available on any jfet input operational amplifier. the lt1055 and lt1056 are differentiated by their operat- ing currents. the lower power dissipation lt1055 achieves lower bias and offset currents and offset voltage. the additional power dissipation of the lt1056 permits higher slew rate, bandwidth and faster settling time with a slight sacrifice in dc performance. the voltage-to-frequency converter shown below is one of the many applications which utilize both the precision and high speed of the lt1055/lt1056. for a jfet input op amp with 23v/ s guaranteed slew rate, refer to the lt1022 data sheet. distribution of input offset voltage (h package) 1hz to 10khz voltage-to-frequency converter input offset voltage ( v) 0 number of units 20 60 80 100 140 400 0 200 lt1055/56 ta02 40 120 400 200 v s = 15v t a = 25 c 634 units tested from three runs 50% to 60 v applicatio s u features typical applicatio u descriptio u , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
2 lt1055/lt1056 10556fc supply voltage ...................................................... 20v differential input voltage ....................................... 40v input voltage ......................................................... 20v output short-circuit duration .......................... indefinite operating temperature range lt1055am/lt1055m/lt1056am/ lt1056m (obsolete) .............. ?5 c to 125 c absolute m axi m u m ratings w ww u package/order i n for m atio n w u u order part number lt1055s8 lt1056s8 1 2 3 4 8 7 6 5 top view bal ?n + in v n/c v + out bal n8 package 8-lead pdip t jmax = 150 c, ja = 130 c/ w lt1055ach lt1055ch lt1055amh lt1055mh top view nc balance out balance + in v 8 7 6 5 3 2 1 4 h package 8-lead to-5 metal can ?n v + t jmax = 150 c, ja = 150 c/ w, jc = 45 c/ w order part number obsolete package consider the n8 package for alternate source (note 1) 1 2 3 4 8 7 6 5 top view s8 package 8-lead plastic so bal ?n + in v n/c v + out bal lt1055cn8 lt1056cn8 order part number t jmax = 150 c, ja = 150 c/ w lt1056ach lt1056ch lt1056amh lt1056mh t a = 25 c. v s = 15v, v cm = 0v unless otherwise noted. electrical characteristics lt1055m/lt1056m lt1055am/lt1056am lt1055ch/lt1056ch lt1055ac/lt1056ac lt1055cn8/lt1056cn8 symbol parameter conditions min typ max min typ max units v os input offset voltage (note 2) lt1055 h package 50 150 70 400 v lt1056 h package 50 180 70 450 v lt1055 n8 package 120 700 v lt1056 n8 package 140 800 v i os input offset current fully warmed up 2 10 2 20 pa lt1055ac/lt1055c/lt1056ac/ lt1056c ................................................ 0 c to 70 c storage temperature range all devices ...................................... 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c 1055 1056 s8 part marking consult ltc marketing for parts specified with wider operating temperature ranges. order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
3 lt1055/lt1056 10556fc lt1055m/lt1056m lt1055am/lt1056am lt1055ch/lt1056ch lt1055ac/lt1056ac lt1055cn8/lt1056cn8 symbol parameter conditions min typ max min typ max units i b input bias current fully warmed up 10 50 10 50 pa v cm = 10v 30 130 30 150 pa input resistance:differential 10 12 10 12 ? common mode v cm = 11v to 8v 10 12 10 12 ? v cm = 8v to 11v 10 11 10 11 ? input capacitance 4 4 pf e n input noise voltage 0.1hz to 10hz lt1055 1.8 2.0 v p-p lt1056 2.5 2.8 v p-p input noise voltage density f 0 = 10hz (note 3) 28 50 30 60 nv/ hz f 0 = 1khz (note 4) 14 20 15 22 nv/ hz i n input noise current density f 0 = 10hz, 1khz (note 5) 1.8 4 1.8 4 fa/ hz a vol large-signal voltage gain v 0 = 10v r l = 2k 150 400 120 400 v/mv r l = 1k 130 300 100 300 v/mv input voltage range 11 12 11 12 v cmrr common mode rejection ratio v cm = 11v 861008398 db psrr power supply rejection ratio v s = 10v to 18v 90 106 88 104 db v out output voltage swing r l = 2k 12 13.2 12 13.2 v sr slew rate lt1055 10 13 7.5 12 v/ s lt1056 12 16 9.0 14 v/ s gbw gain bandwidth product f = 1mhz lt1055 5.0 4.5 mhz lt1056 6.5 5.5 mhz i s supply current lt1055 2.8 4.0 2.8 4.0 ma lt1056 5.0 6.5 5.0 7.0 ma offset voltage adjustment range r pot = 100k 5 5mv t a = 25 c. v s = 15v, v cm = 0v unless otherwise noted. electrical characteristics lt1055ac lt1055ch/lt1056ch lt1056ac lt1055cn8/lt1056cn8 symbol parameter conditions min typ max min typ max units v os input offset voltage (note 2) lt1055 h package 100 330 140 750 v lt1056 h package 100 360 140 800 v lt1055 n8 package 250 1250 v lt1056 n8 package 280 1350 v average temperature h package (note 6) 1.2 4.0 1.6 8.0 v/ c coefficient of input offset n8 package (note 6) 3.0 12.0 v/ c voltage i os input offset current warmed up lt1055 10 50 16 80 pa t a = 70 c lt1056 14 70 18 100 pa i b input bias current warmed up lt1055 30 150 40 200 pa t a = 70 c lt1056 40 80 50 240 pa a vol large-signal voltage gain v o = 10v, r l = 2k 80 250 60 250 v/mv cmrr common mode rejection ratio v cm = 10.5v 851008298 db psrr power supply rejection ratio v s = 10v to 18v 89 105 87 103 db v out output voltage swing r l = 2k 12 13.1 12 13.1 v the denotes the specifications which apply over the temperature range 0 c t a 70 c. v s = 15v, v cm = 0v unless otherwise noted.
4 lt1055/lt1056 10556fc lt1055am lt1055m lt1056am lt1056m symbol parameter conditions min typ max min typ max units v os input offset voltage (note 2) lt1055 180 500 250 1200 v lt1056 180 550 250 1250 v average temperature (note 6) 1.3 4.0 1.8 8.0 v/ c coefficient of input offset voltage i os input offset current warmed up lt1055 0.20 1.2 0.25 1.8 na t a = 125 c lt1056 0.25 1.5 0.30 2.4 na i b input bias current warmed up lt1055 0.4 2.5 0.5 4.0 na t a = 125 c lt1056 0.5 3.0 0.6 5.0 na a vol large-signal voltage gain v o = 10v, r l = 2k 40 120 35 120 v/mv cmrr common mode rejection ratio v cm = 10.5v 851008298 db psrr power supply rejection ratio v s = 10v to 17v 88 104 86 102 db v out output voltage swing r l = 2k 12 12.9 12 12.9 v electrical characteristics the denotes the specifications which apply over the temperature range ?5 c t a 125 c. v s = 15v, v cm = 0v, unless otherwise noted. t a = 25 c. v s = 15v, v cm = 0v unless otherwise noted. lt1055cs8/lt1056cs8 symbol parameter conditions min typ max units v os input offset voltage (note 2) 500 1500 v i os input offset current fully warmed up 5 30 pa i b input bias current fully warmed up 30 100 pa v cm = 10v 30 150 pa input resistance differential 0.4 t ? common mode v cm = ?1v to 8v 0.4 t ? v cm = 8v to 11v 0.05 t ? input capacitance 4pf e n input noise voltage 0.1hz to 10hz lt1055 2.5 v p-p lt1056 3.5 v p-p input noise voltage density f o = 10hz (note 4) 35 70 nv/ hz f o = 1khz (note 4) 15 22 nv/ hz i n input noise current density f o = 10hz, 1khz (note 5) 2.5 10 fa/ hz a vol large-signal voltage gain v o = 10v r l = 2k 120 400 v/mv r l = 1k 100 300 v/mv input voltage range 11 12 v cmrr common mode rejection ratio v cm = 11v 83 98 db psrr power supply rejection ratio v s = 10v to 18v 88 104 db v out output voltage swing r l = 2k 12 13.2 v sr slew rate lt1055 7.5 12 v/ s lt1056 9.0 14 v/ s gbw gain bandwidth product f = 1mhz lt1055 4.5 mhz lt1056 5.5 mhz i s supply current lt1055 2.8 4.0 ma lt1056 5.0 7.0 ma offset voltage adjustment range r pot = 100k 5mv
5 lt1055/lt1056 10556fc for mil-std components, please refer to ltc883 data sheet for test listing and parameters. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: offset voltage is measured under two different conditions: (a) approximately 0.5 seconds after application of power; (b) at t a = 25 c only, with the chip heated to approximately 38 c for the lt1055 and to 45 c for the lt1056, to account for chip temperature rise when the device is fully warmed up. note 3: 10hz noise voltage density is sample tested on every lot of a grades. devices 100% tested at 10hz are available on request. note 4: this parameter is tested on a sample basis only. note 5: current noise is calculated from the formula: i n = (2ql b ) 1/2 , where q = 1.6 ?10 ?9 coulomb. the noise of source resistors up to 1g ? swamps the contribution of current noise. note 6: offset voltage drift with temperature is practically unchanged when the offset voltage is trimmed to zero with a 100k potentiometer between the balance terminals and the wiper tied to v + . devices tested to tighter drift specifications are available on request. electrical characteristics the denotes the specifications which apply over the temperature range 0 c t a 70 c. v s = 15v, v cm = 0v, unless otherwise noted. lt1055cs8/lt1056cs8 symbol parameter conditions min typ max units v os input offset voltage (note 2) 800 2200 v average temperature coefficient of input offset voltage 415 v/ c i os input offset current warmed up, t a = 70 c 18 150 pa i b input bias current warmed up, t a = 70 c 60 400 pa a vol large-signal voltage gain v o = 10v, r l = 2k 60 250 v/mv cmrr common mode rejection ratio v cm = 10.5v 82 98 db psrr power supply rejection ratio v s = 10v to 18v 87 103 db v out output voltage swing r l = 2k 12 13.1 v
6 lt1055/lt1056 10556fc typical perfor m a n ce characteristics u w 0.1hz to 10hz noise warm-up drift distribution of offset voltage drift with temperature (h package)* long term drift of representative units time (seconds) 0 noise voltage (1 v/division) 8 lt1055/56 go7 2 4 6 10 lt1056 lt1055 rms noise voltage density (nv/ hz) frequency (hz) 1 100 30 300 lt1055/56 g09 30 10 3 10 100 300 1000 1000 lt1056 1/f corner = 28hz lt1055 1/f corner = 20hz v s = 15v t a = 25 c voltage noise vs frequency noise vs chip temperature chip temperature ( c) 20 1 2 3 5 7 10 10 20 30 50 70 100 40 lt1055/56 g08 0.1hz to 10hz peak-to-peak noise ( v/ p-p ) 10 80 30 50 60 70 f 0 = 10khz f 0 = 1khz peak-to-peak noise rms noise voltage density (nv/ hz) offset voltage drift with temperature ( v/ c) ?0 0 battery voltage (v) 20 60 80 100 140 ? 0 4 lt1055/56 g04 40 120 ? 8 10 ? ? 26 *distribution in the plastic (n8) package is significantly wider. v s = 15v 634 units tested from three runs 50% to 1.5 v/ c time after power on (minutes) 0 change in offset voltage ( v) 60 80 100 4 lt1055/56 g05 40 20 0 1 2 3 5 v s = 15v t a = 25 c lt1056cn8 lt1055cn8 lt1056 h package lt1055 h package time (months) 0 offset voltage change v) 50 ?0 40 ?0 30 ?0 20 ?0 10 ?0 0 4 lt1055/56 go6 1 2 3 5 v s = 15v t a = 25 c lt1055/56 g02 common mode input voltage (v) ?5 120 input bias current, t a = 25 c, t a = 70 c (pa) ?0 ?0 0 40 120 ?0 5 0 5 10 15 80 1200 800 400 0 400 1200 800 v s = 15v warmed up t a = 125 c t a = 125 c t a = 25 c t a = 70 c t a = 70 c a = positive input current b = negative input current a b b a input bias current, t a = 125 c (pa) input bias and offset currents vs temperature ambient temperature ( c) 0 input bias and offset current (pa) 100 300 1000 100 lt1055/56 g01 30 10 3 25 50 75 125 bias or offset currents may be positive or negative bias current offset current v s = 15v v cm = 0v warmed up input bias current over the common mode range distribution of input offset voltage (n8 package) input offset voltage ( v) 800 number of inputs 80 100 120 800 lt1055/56 g03 60 40 0 400 0 400 20 160 140 600 200 200 600 v s = 15v t a = 25 c 550 units tested from two runs (lt1056) 50% yield to 140 v
7 lt1055/lt1056 10556fc a v = 1, c l = 100pf, 0.5 s/div 5v/div lt1056 large-signal response typical perfor m a n ce characteristics u w lt1055/56 g10 lt1055/56 g12 a v = 1, c l = 100pf, 0.5 s/div 5v/div undistorted output swing vs frequency output impedence vs frequency frequency (khz) 1 0.1 output impedance ( ? ) 1 10 100 10 100 1000 lt1055/56 g15 v s = 15v t a = 25 c a v = 100 lt1055 lt1056 lt1055 lt1056 lt1056 a v = 10 lt1055 a v = 1 gain vs frequency frequency (hz) 1 gain (db) 60 80 100 100m lt1055/56 g16 40 20 ?0 100 10k 1m 0 140 120 10 1k 100k 10m v s = 15v t a = 25 c lt1055 lt1056 temperature ( c) ?5 10 100 30 1000 300 25 75 lt1055/56 g18 voltage gain (v/mv) ?5 125 r l = 1k r l = 2k v s = 15v v o = 10v voltage gain vs temperature frequency (mhz) 0.1 0 peak-to-peak output swing (v) 6 12 18 24 110 lt1055/56 g13 30 lt1055 lt1056 v s = 15v t a = 25 c frequency (mhz) 1 gain (db) phase shift (degrees) 10 10 lt1055/56 g17 0 ?0 2 4 20 100 120 140 160 6 8 v s = 15v t a = 25 c phase gain lt1055 lt1056 lt1055 lt1056 small-signal response 20mv/div a v = 1, c l = 100pf, 0.2 s/div lt1055/56 g11 slew rate, gain bandwidth vs temperature gain, phase shift vs frequency temperature (?c) slew rate (v/ s) gain bandwidth product (mhz) 20 30 25 75 lt1055/56 g14 10 ?5 125 0 10 8 6 4 2 v s = 15v f 0 = 1mhz for gbw lt1056 gbw lt1055 gbw lt1055 slew lt1056 slew lt1055 large-signal response
8 lt1055/lt1056 10556fc supply voltage (v) 0 supply current (ma) 4 6 20 lt1055/56 g25 2 0 5 10 15 8 t a = 55 c t a = 125 c t a = 55 c t a = 125 c lt1056 lt1055 25 c 25 c load resistance (k ? ) 0.1 0.3 ?5 output voltage swing (v) ? ?2 ? ? 3 0 9 6 13 10 lt1055/56 g26 15 12 t a = 25 c t a = ?25 c t a = 55 c t a = 55 c t a = 25 c t a = ?25 c v s = 15v typical perfor m a n ce characteristics u w lt1055 settling time settling time ( s) 0 output voltage swing from 0v (v) 0 lt1055/56 g19 ? ?0 12 5 10 3 10mv 10mv 0.5mv 1mv 5mv 5mv 2mv 1mv 0.5mv v s = 15v t a = 25 c 2mv power supply rejection ratio vs frequency frequency (hz) 10 80 100 120 10k 1m lt1055/56 g24 60 40 100 1k 100k 10m 20 0 power supply rejection ratio (db) 140 t a = 25 c positive supply negative supply common mode range vs temperature temperature ( c) ?0 ?5 battery voltage (v) ?4 ?2 ?1 10 15 12 0 50 100 lt1055/56 g21 ?3 13 14 11 v s = 15v settling time ( s) 0 output voltage swing from 0v (v) 0 lt1055/56 g20 ? ?0 12 5 10 3 10mv 10mv 2mv 0.5mv 1mv 5mv 5mv 2mv 1mv 0.5mv v s = 15v t a = 25 c lt1056 settling time temperature (?c) cmrr, psrr (db) 110 120 25 75 lt1055/56 g22 100 ?5 125 90 v s = 10v to 17v for psrr v s = 15v, v cm = 10.5v for cmrr cmrr psrr common mode and power supply rejections vs temperature common mode rejection ratio vs frequency frequency (hz) 10 0 cmrr (db) 20 40 60 80 120 100 1k 10k 100k lt1055/56 g23 1m 10m 100 v s = 15v t a = 25 c short-circuit current vs time time from output short to ground (minutes) 0 ?0 short-circuit current (ma) ?0 ?0 ?0 0 50 20 1 2 lt1055/56 g27 ?0 30 40 10 3 t a = 55 c t a = 25 c t a = 125 c t a = 125 c t a = 25 c t a = 55 c sinking v s = 15v output swing vs load resistance supply current vs supply voltage
9 lt1055/lt1056 10556fc applicatio n s i n for m atio n wu u u the lt1055/lt1056 may be inserted directly into lf155a/ lt355a, lf156a/lt356a, op-15 and op-16 sockets. off- set nulling will be compatible with these devices with the wiper of the potentiometer tied to the positive supply. no appreciable change in offset voltage drift with tempera- ture will occur when the device is nulled with a potentiom- eter, r p , ranging from 10k to 200k. the lt1055/lt1056 can also be used in lf351, lf411, ad547, ad611, opa-111, and tl081 sockets, provided that the nulling cicuitry is removed. because of the lt1055/ lt1056? low offset voltage, nulling will not be necessary in most applications. achieving picoampere/microvolt performance in order to realize the picoampere-microvolt level accu- racy of the lt1055/lt1056 proper care must be exer- cised. for example, leakage currents in circuitry external to the op amp can significantly degrade performance. high quality insulation should be used (e.g. teflon, kel-f); cleaning of all insulating surfaces to remove fluxes and other residues will probably be required. surface coating may be necessary to provide a moisture barrier in high humidity environments. board leakage can be minimized by encircling the input circuitry with a guard ring operated at a potential close to that of the inputs: in inverting configurations the guard ring should be tied to ground, in noninverting connnections to the inverting input at pin 2. guarding both sides of the printed circuit board is required. bulk leakage reduction depends on the guard ring width. offset nulling the lt1055/lt1056 has the lowest offset voltage of any jfet input op amp available today. however, the offset voltage and its drift with time and temperature are still not as good as on the best bipolar amplifiers because the transconductance of fets is considerably lower than that of bipolar transistors. conversely, this lower transcon- ductance is the main cause of the significantly faster speed performance of fet input op amps. offset voltage also changes somewhat with temperature cycling. the am grades show a typical 20 v hysteresis (30 v on the m grades) when cycled over the 55 c to 125 c temperature range. temperature cycling from 0 c to 70 c has a negligible (less than 10 v) hysteresis effect. the offset voltage and drift performance are also affected by packaging. in the plastic n8 package the molding compound is in direct contact with the chip, exerting pressure on the surface. while npn input transistors are largely unaffected by this pressure, jfet device matching and drift are degraded. consequently, for best dc perfor- mance, as shown in the typical performance distribution plots, the to-5 h package is recommended. noise performance the current noise of the lt1055/lt1056 is practically immeasurable at 1.8fa/ hz. at 25 c it is negligible up to 1g of source resistance, r s (compound to the noise of r s ). even at 125 c it is negligible to 100m of r s . lt1055/56 ai2 offset trim offset trim n/c guard output inputs v + v 1 8 7 6 5 4 3 2 + v + v out 2 3 4 1 5 7 r p 6 lt1055/56 ai1 lt1055 lt1056 teflon is a trademark of dupont.
10 lt1055/lt1056 10556fc applicatio n s i n for m atio n wu u u the voltage noise spectrum is characterized by a low 1/f corner in the 20hz to 30hz range, significantly lower than on other competitive jfet input op amps. of particular interest is the fact that with any jfet ic amplifier, the frequency location of the 1/f corner is proportional to the square root of the internal gate leakage currents and, therefore, noise doubles every 20 c. furthermore, as illustrated in the noise versus chip temperature curves, the 0.1hz to 10hz peak-to-peak noise is a strong function of temperature, while wideband noise (f 0 = 1khz) is practically unaffected by temperature. consequently, for optimum low frequency noise, chip temperature should be minimized. for example, operating an lt1056 at 5v supplies or with a 20 c/w case-to- ambient heat sink reduces 0.1hz to 10hz noise from typically 2.5 v p-p ( 15v, free-air) to 1.5 v p-p . similiarly, the noise of an lt1055 will be 1.8 v p-p typically because of its lower power dissipation and chip temperature. high speed operation settling time is measured in the test circuit shown. this test configuration has two features which eliminate prob- lems common to settling time measurments: (1) probe capacitance is isolated from the ?alse summing?node, and (2) it does not require a ?lat top?input pulse since the input pulse is merely used to steer current through the diode bridges. for more details, please see application note 10. as with most high speed amplifiers, care should be taken with supply decoupling, lead dress and component placement. when the feedback around the op amp is resistive (r f ), a pole will be created with r f , the source resistance and capacitance (r s , c s ), and the amplifier input capacitance (c in 4pf). in low closed-loop gain configurations and with r s and r f in the kilohm range, this pole can create excess phase shift and even oscillation. a small capacitor (c f ) in parallel with r f eliminates this problem. with r s (c s + c in ) = r f c f , the effect of the feedback pole is completely removed. 0.01 disc + + + + + + 15v 15v 15v 15v 15k 15k 15k 15k 10k 4.7k 4.7k 10 f solid tantalum 10 f solid tantalum 10 f solid tantalum 10 f solid tantalum 10pf (typical) 10k pulse gen input (5v min step) 2k 2k 0.01 disc 0.01 disc 0.01 disc 50 ? 2w lt1055 lt1056 amplifier under test aut output hp5082-8210 hewlett packard 15v 15v 15v 15v = 1n4148 15v 15v 1/2 u440 1/2 u440 50 ? 3 ? 3 ? 100 ? dc zero 2n160 2n5160 2n3866 2n3866 lt1055/56 ai04 output to scope settling time test circuit + r s r f c f c s c in output lt1055/56 ai03
11 lt1055/lt1056 10556fc applicatio n s i n for m atio n wu u u phase reversal protection most industry standard jfet input op amps (e.g., lf155/ lf156, lf351, lf411, op15/16) exhibit phase reversal at the output when the negitive common mode limit at the input is exceeded (i.e., from 12v to 15v with 15v supplies). this can cause lock-up in servo systems. as shown below, the lt1055/lt1056 does not have this problem due to unique phase reversal protection circuitry (q1 on simplified schematic). 0.5ms/div 0.5ms/div 0.5ms/div 10v/div 10v/div 10v/div lt1055/56 ai06 lt1055/56 ai07 lt1055/56 ai08 typical applicatio n s u ? exponential voltage-to-frequency converter for music synthesizers input 0v to 10v lt1055/56 ta03 + 11.3k* exponent trim 2500 ? * 562 ? * 3.57k* zero trim 15v 500k 500 ? * 4.7k 1.1k 10k* 3k 10k* 1k* 1k* 4.7k 2 3 4 5 6 15v 15v 7 lt1055 15v 500pf polystyrene 6 2 3 15v 7 lm301a 15v 6 8 2n3906 2n3904 sawtooth output lm329 0.01 f 1 4 2 3 1 1n148 13 14 15 2.2k 9 7 8 33 ? temperature control loop scale factor 1v in octave out *1% metal film resistor pin numbered transistors = ca3096 array + ? for ten additional applications utilizing the lt1055 and lt1056, please see the ltc1043 data sheet and application note 3. voltage follower with input exceeding the negative common mode range + 2k 15v 15v output 2 3 4 input 15v sine wave 7 6 lt1055/56 lt1055/56 ai05 output lt1055/lt1056 output (lf155/lf56, lf441, op-15/op-16) input
12 lt1055/lt1056 10556fc fast, 16-bit current comparator + + 2 15v 7 6 3 15v lt1056 4.7k 50k* input lt1009 2.5v 100k* 4 ?5v 2 hp5082-2810 8 15v 3k output 1 7 4 ?5v lt1011 3 delay = 250ns * = 1% film resistor lt1055/56 ta06 12-bit charge balance a/d converter + + 28k 33k 14k 74c00 0.003 f clk output (b) 10k output (a) d p cl q q clk 74c74 1n4148 0.01 2 15v 15v 7 4 6 3 1n4148 1n4148 15v 10k 2n3904 249k* 0v to 10v input couple thermally 1n4148 6 33k lm329 10k 15v 2 3 7 4 15v 15v lt1055/56 ta04 lt1055 lt1001 circuit output ratio f out (a) f clk (b) fast ?o trims?12-bit multiplying cmos dac amplifier lt1055/56 ta05 r feedback i out1 i out2 output reference in typical 12-bit cmos dac + lt1055 typical applicatio s u
13 lt1055/lt1056 10556fc typical applicatio s u temperature-to-frequency converter lt1055/56 ta07 2 3 15v 7 4 6 lt1055 15v 15v 560 ? 15v + lm329 510 ? 820 ? * 6.2k* 500 ? 0 c adj 2k 100 c adj 6.2k* 1k* 1k* 2n2907 2n2222 0.01 f polystyrene 510pf 2.7k 10k 10k 4.7k 2n2222 ttl output 0khz to 1khz = 0 c to 100 c 2v lm134 137 ? * *1% film resistor 100khz voltage controlled oscillator + + + + x1 x2 u1 u2 com vr y1 y2 + v cc w z1 z2 gt up ? + 15v sine out 2v rms 0khs to 100khs ?5 ad639 2 3 15v 7 6 4 15v 15v 68k 68k 10k 4.5k 22.1k 1k lt1056 fine distortion trims 15v 15v 15v 15v 15v 15v 15v 15v lt1055/56 ta08 50k 10hz distortion trim 22m polystyrene 500pf 7 4 3 2 6 lt1056 22k 15pf hp5082- 2810 3 2 10k* 10k 1k 4.7k 4.7k *1% film resistor =1n4148 frequency linearity = 0.1% frequency stability = 150ppm/ c settling time = 1.7 s distortion = 0.25% at 100khz, 0.07% at 10zhz 1k 5k frequency trim lt1011 8 7 1 4 lm329 0.01 f 2.5k* 10k* 5k* 2n4391 2n4391 2n4391 6 7 4 15v 15v lt1056 100khz distortion trim 2k 9.09k* 0v to 10v input 2 3 10k 20pf
14 lt1055/lt1056 10556fc 1 3 2 null 5 7 6 output null input + input 7k 7k j6 j7 j4 j3 j8 j5 j1 j2 q7 q3 q4 q8 q9 q2 q1 q14 q12 q11 q10 q13 q15 q16 400 a* (1100) q5 7.5pf 300 ? 50 ? 3k v + 4 v 20 ? 200 ? 800 a* (1000) 120 a* (160) 120 a* (160) 8k 14k 14k 9pf *currents as shown for lt1055. (x) = currents for lt1056. lt1055/56 schm sche atic w w si plified typical applicatio s u + 15v 15v 7 4 3 2 6 lt1056 output 0v to 10v c f = 15pf to 33pf settling time to 2mv (0.8 lsb) = 1.5 s to 2 s 0 to 2 or 4ma 12-bit current output d/a converter (e.g., 6012,565 or dac-80) c f lt1055/56 ta09 12-bit voltage output d/a converter
15 lt1055/lt1056 10556fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u h package 8-lead to-5 metal can (.200 inch pcd) (reference ltc dwg # 05-08-1320) n8 package 8-lead pdip (narrow .300 inch) (reference ltc dwg # 05-08-1510) 0.050 (1.270) max 0.016 ?0.021** (0.406 ?0.533) 0.010 ?0.045* (0.254 ?1.143) seating plane 0.040 (1.016) max 0.165 ?0.185 (4.191 ?4.699) gauge plane reference plane 0.500 ?0.750 (12.700 ?19.050) 0.305 ?0.335 (7.747 ?8.509) 0.335 ?0.370 (8.509 ?9.398) dia 0.200 (5.080) typ 0.027 ?0.045 (0.686 ?1.143) 0.028 ?0.034 (0.711 ?0.864) 0.110 ?0.160 (2.794 ?4.064) insulating standoff 45 typ h8(to-5) 0.200 pcd 1197 lead diameter is uncontrolled between the reference plane and 0.045" below the reference plane for solder dip lead finish, lead diameter is 0.016 ?0.024 (0.406 ?0.610) * ** pin 1 obsolete package n8 1002 .065 (1.651) typ .045 ?.065 (1.143 ?1.651) .130 .005 (3.302 0.127) .020 (0.508) min .018 .003 (0.457 0.076) .120 (3.048) min 12 3 4 87 6 5 .255 .015* (6.477 0.381) .400* (10.160) max .008 ?.015 (0.203 ?0.381) .300 ?.325 (7.620 ?8.255) .325 +.035 ?015 +0.889 0.381 8.255 () note: 1. dimensions are inches millimeters *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 inch (0.254mm) .100 (2.54) bsc
16 lt1055/lt1056 10556fc lt 0406 rev c ? printed in usa ? linear technology corporation 1994 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com 10k 10k 100pf lt1055/56 ta10 + 7 4 3 2 6 lt1055 10k input 1n965 1 f 510 ? 330 ? 125v 2n5415 50k 50k 1m 1m 1n4148 1n4148 2n2222 2n2907 1k 1k 2n3440 27 ? 27 ? output 2n5415 2n3440 330 ? 510 ? 1n965 1 f 125v 33pf 100k 10k 25ma output heat sink output transistors 120v output precision op amp typical applicatio u related parts part number description comments lt1122 fast settling jfet op amp 340ns settling time, gbw = 14mhz, sr = 60v/ s lt1792 low noise jfet op amp e n = 6nv/ hz max at f = 1khz package descriptio u s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) so8 0303 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc 1 2 3 4 .150 ?.157 (3.810 ?3.988) note 3 8 7 6 5 .189 ?.197 (4.801 ?5.004) note 3 .228 ?.244 (5.791 ?6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)

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